(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the elimination of copper line damage for damascene processing, by depositing a multilayer interface material, consisting of a mechanically hard film and a soft film, over a low dielectric constant, interlevel metal dielectric (IMD), and subsequently chemical mechanical polishing (CMP) back the excess material to planarize the surface.
(2) Description of Related Art
As an introduction and background to Prior Art, the conventional dual damascene process scheme is commonly used to fabricate of copper interconnects, trench, and contact vias. Dual Damascene wiring interconnects (and/or studs) are formed by depositing one or two dielectric layers on a planar surface, patterning it using photolithography and dielectric reactive ion etch (RIE), then filling the recesses with conductive copper metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with inlaid metal. With the dual damascene process, two layers of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 6,004,188 entitled xe2x80x9cMethod for Forming Copper Damascene Structures by Using a Dual CMP Barrier Layerxe2x80x9d granted Dec. 21, 1999 to Roy describes a method for forming copper damascene structures by using a dual chemical mechanical polish (CMP) barrier layer. The polishing barrier layers consist of a bottom layer of TiN with a layer of Ta or TaN on top of the TiN layer. The top layer has a low polishing rate, while the bottom layer has a high polishing rate similar to that of copper. Dishing of copper lines and interconnects is avoided by this method.
U.S. Pat. No. 6,010,962 entitled xe2x80x9cCopper Chemical Mechanical Polishing (CMP) Dishingxe2x80x9d granted Jan. 4, 2000 to Lui et al. shows Chemical-Mechanical Polish (CMP) planarizing method that avoids dishing. A conformal blanket barrier layer is formed over the substrate including the already formed trench/via regions. A copper seed layer is grown over the barrier layer. A layer of photoresist is deposited over the substrate filling the composite structure. These layers are then chemical mechanical polished (CMP) back to planarize the surface leaving both the seed layer and barrier layer on the walls of the trench/via. The photoresist is removed and is replaced by electroless plated copper, which forms a xe2x80x9cdome-likexe2x80x9d structures that prevents dishing.
U.S. Pat. No. 5,512,163 entitled xe2x80x9cMethod for Forming a Planarization Etch Stopxe2x80x9d granted Apr. 30, 1996 to Warfield shows mechanical polishing method that uses an etch-stop layer consisting of a metal and grit material, i.e., diamond powder, over a conductive layer.
U.S. Pat. No. 5,854,133 entitled xe2x80x9cMethod for Manufacturing a Semiconductor Devicexe2x80x9d granted Dec. 29, 1998 to Hachiya et al. shows chemical mechanical polish (CMP) planarizing method that utilizes a polysilicon film as an etch-stop. A carbon film is also used an etch-stop, in conjunction with an insulation film, which is planarized on a silicon substrate.
It is a general object of the present invention to provide an improved method of forming an integrated circuit in which copper line damage is eliminated for damascene processing, by depositing a multilayer interface material, consisting of a mechanically hard film and a soft film, over a low dielectric constant, interlevel metal dielectric (IMD), and subsequently chemical mechanical polishing (CMP) back the excess material to planarize the surface. An outline of the key process steps of this invention follow.
Low dielectric constant material is deposited, as an intermetal dielectric (IMD) layer, over the substrate, to subsequently form dual damascene trench/via openings. The low dielectric constant material, as an intermetal dielectric layer (IMD) or layers, and in general, the insulating layers, are selected from the group comprised of xe2x80x9cSILK C. H.O. (polymer based)xe2x80x9d, Flare and other low-k polymer materials, silicon dioxide or silicon oxide, and/or silicon nitride. The key multilayer interface layer is deposited over the intermetal dielectric layer, comprised of a bottom hard film layer, which is selected from the group comprised of silicon nitride, silicon oxynitride, and silicon carbide. Next, the second part of multilayer interface layer is deposited. This second part of the multilayer interface layer is comprised of a top soft film layer, which is selected from the group comprised of silicon oxide, plasma enhanced (PE) oxide, plasma enhanced (PE) TEOS, tetraethylorthosilicate, and low dielectric constant polymer materials. Hence, the multilayer interface layer is comprised of a bottom hard film layer and a top soft film layer. However, the reversal of these layers, namely a soft layer first, bottom layer, and a hard layer second, top layer, is just as effect. Next, a dielectric anti-reflective coating (DARC) is place over the multilayer interface layer and this DARC layer is selected from the group comprised of silicon oxynitride, and is deposited by chemical vapor deposition (CVD), over the multilayer interface layer. A layer of photoresist is patterned over the DARC and multilayer interface layer.
Next, the excess copper and the other top layer materials are planarized forming in the damascene and dual damascene patterned openings, inlaid copper metal, by removing excess conducting material to form inlaid dual damascene conducting metal interconnects, in trench and via openings, by chemical mechanical polishing (CMP) the inlaid copper metal layer, by removing the excess copper metal layers including excess copper seed layer, the excess barrier layer, and the excess multilevel interface layer, including the dielectric anti-reflective coating (DARC). Thus the surface is planarized by chemical mechanical polishing (CMP), forming smooth surface inlaid copper, which remains in the open regions.
Note, the processes described in this invention are compatible with MOSFET CMOS processing, for CMOS devices and circuits, in both logic and memory applications. The hard film layer polishing properties, materials consisting of silicon nitride, silicon oxynitride and silicon carbide, have a slower polishing removal rate than that of copper. The soft film layer polishing properties, materials consisting of silicon oxide, plasma enhanced (PE) oxide, plasma enhanced (PE) TEOS, tetraethylorthosilicate and low dielectric constant polymer materials, have a faster polishing removal rate than that of copper.
Data is presented which shows a comparison of soft and hard interface layers, with multilayer interface layers for chemical mechanical polishing (CMP) of copper, presenting dishing, erosion and non-uniformity data. The main area highlighted for this present invention, contain the data for interface layers soft and hard, and hard and soft, upon a xe2x80x9cSILK C.H.O. (polymer based)xe2x80x9d, low dielectric layer. The interface layers for these two bottom categories of plasmas enhanced oxide (PEOX) 500 Angstrom thick and silicon oxynitride (SION) 500 Angstroms thick, show low dishing and low erosion. Data is also presented that shows a comparison of soft and hard interface layers, with multilayer interface layers for chemical mechanical polishing (CMP) of copper, copper line damage and defect data. The main area highlighted for this present invention, is the data for interface layers soft and hard, and hard and soft, upon a xe2x80x9cSilk C.H.O. (polymer based)xe2x80x9d, low dielectric layer. The interface layers for these two bottom categories of plasmas enhanced oxide (POX) 500 Angstrom thick and silicon oxynitride (SION) 500 Angstroms thick, show no copper line damage dishing and no defects.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.